1. Field of Invention
The present invention relates to a high-voltage semiconductor device structure, and more particularly, to a lateral-diffused metal oxide semiconductor (LDMOS) device structure.
2. Related Art
An LDMOS device is usually applied in a high voltage operation environment, for example, a power amplifier with a high power or a high frequency band, or a high power device of a base station. The LDMOS has a high voltage resistance characteristic, which is capable of resisting tens to hundreds volts of voltage. The main reason lies in that, the LDMOS has a low-doped drift extension region in the drain extension structure, which is used to relieve the breakdown effect between a drain terminal and a source terminal, thus the device has a relatively high breakdown voltage. In order to provide the LDMOS with a higher breakdown voltage, the structure of the device must be improved.
FIGS. 1A and 1B are respectively an allocation diagram and a sectional view of an LDMOS device structure in the conventional art. As shown in FIG. 1A, the conventional LDMOS 10 structure includes a source structure 11, a drain structure 12, a drain extension structure 13, and a gate structure 14.
The source structure 11 has a protrusion 11′ extending from the lower portion of the source structure 11 to the central portion, and the protrusion 11′ is surrounded by and spaced apart for a predetermined distance with the upper, left, and right side portion of the source structure 11 respectively. The drain structure 12 is disposed in the region formed by the above predetermined distances, and forms an oxbow-shaped region that surrounds the left, upper and right side of the protrusion 11′, and the periphery of the oxbow-shaped region is surrounded by the source structure 11 outside the protrusion 11′. The drain extension structure 13 surrounds the periphery of the drain structure 12 and it is spaced apart for a specific distance with the source structure 11. Meanwhile, a gate structure 14 is provided between the source structure 11 and the drain extension structure 13, and a field effect channel region is provided below the gate structure 14. Under the low ON-resistance (Rdson) requirement of the high voltage device, the layout feature of the protrusion 11′ cannot be easily avoided.
FIG. 1B is a sectional view of FIG. 1A taken alone the line I-I. The source structure 11 includes a source electrode 16 formed on the surface of a substrate (e.g., a p-type substrate 15); a p-type well 17 formed in the p-type substrate 15 and located below the source electrode 16, which is doped with p-type conductive ions; an n+-type doped region 18 formed in the p-type well 17, which is a region having n-type conductive ions with a high doping concentration; a p+-type doped region 19 formed in the p-type well 17 and being adjacent to the n+-type doped region 18, which is a region having p-type conductive ions with a high doping concentration; wherein the n+-type doped region 18 and the p+-type doped region 19 are both connected with the source electrode 16.
The source structure 12 includes a drain electrode 20 formed on the surface of the p-type substrate 15; an n-type well 21 located below the drain electrode 20 and formed in the p-type substrate 15; an n+-type doped region 22 formed in the n-type well, which is a region having n-type conductive ions with a high doping concentration and connected with the drain electrode 20.
The drain extension structure 13 includes an n-type drift extension region 23 having n-type conductive ions with a low doping concentration, and a p-type doped region 24 formed in the n-type drift extension region 23. There is a predetermined distance between the n-type drift extension region 23 of the drain extension structure 13 and the n+-type doped region 18 of the source structure 11, to form a field effect channel region 27.
The gate structure 14 includes a gate insulation layer 25 formed on the surface of the substrate and a gate electrode 26 formed on the gate insulation layer 25. The gate structure 14 is disposed above the n-type drift extension region 23 and the p-type well 17, and the field effect channel region 27 is turned on/off by controlling the gate voltage.
In the above LDMOS structure, the source protrusion 11′ has a tip 111 with a small curvature radius which easily produces a charge accumulation phenomenon and makes the intensity of the electric field passing through this portion become stronger, thus, the electric field in the field effect channel region is non-uniformly distributed. During the operation under a high voltage, a breakdown effect occurs due to a local accumulation effect of the electric field, thus, the breakdown voltage of the LDMOS is reduced. If it is intended that the breakdown voltage of the device is not affected by the protrusion 11′, the curvature radius must be increased. However, the overall area of the device is enlarged accordingly, and correspondingly, the ON-resistance (Rdson) is increased, and the integration of the device on the chip is reduced.